Addition in semiconductor arithmetic circuits was conducted, in conventional binary digital processing, by partitioning inputted data (in this specification, `data` refers to a complete inputted item comprising a plurality of bits) by the data bit (`bit` indicates a 1-place binary number), and processing this; this was realized by using full adder elements.
Since full adder elements are elements having 3 inputs and 2 outputs, if one of the inputs is used as a carry signal, it is possible to construct a system capable of processing 2 item calculations without difficulty.
However, in the case of addition of multiple items, it is necessary to combine full adders in a number of stages, and it is impossible to avoid an increase in complexity and scale of the circuits. Multiple item addition processing is required in a variety of fields; however, in particular, as multiplication of four rules operations is also realized by multiple rounds of addition, such multiple item addition calculations are necessary in operational processing, and the development of a multiple item addition basic element which can take the place of the full adder has been desired.
The present invention has as an object thereof to provide a semiconductor arithmetic circuit which is capable of realizing multiple item addition processing at high speeds or using a small surface area.